Modern electronics, such as smart phones, personal digital assistants, location based services devices, digital cameras, music players, servers, and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. One cornerstone for electronics to continue proliferation into everyday life is the non-volatile storage of information such as cellular phone numbers, digital pictures, or music files. Numerous technologies have been developed to meet these requirements.
Various types of non-volatile memories have been developed including electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). Each type of memory had advantages and disadvantages. EEPROM can be easily erased without extra exterior equipment but with reduced data storage density, lower speed, and higher cost. EPROM, in contrast, is less expensive and has greater density but lacks erasability.
A newer type of memory called “Flash” EEPROM, or Flash memory, has become popular because it combines the advantages of the high density and low cost of EPROM with the electrical erasability of EEPROM. Flash memory can be rewritten and can hold its contents without power. Contemporary Flash memories are designed in a floating gate or a charge trapping architecture. Each architecture has its advantages and disadvantages.
The floating gate architecture offers implementation simplicity. This architecture embeds a gate structure, called a floating gate, inside a conventional metal oxide semiconductor (MOS) transistor gate stack. Electrons can be injected and stored in the floating gate as well as erased using an electrical field or ultraviolet light. The stored information may be interpreted as a value “0” or “1” from the threshold voltage value depending upon charge stored in the floating gate. As the demand for Flash memories increases, the Flash memories must scale with new semiconductor processes. However, new semiconductor process causes a reduction of key feature sizes in Flash memories of the floating gate architecture which results in decrease in data retention.
The charge trapping architecture offers improved scalability to new semiconductor processes compared to the floating gate architecture. One implementation of the charge trapping architecture is a silicon-oxide-nitride-oxide semiconductor (SONOS) where the charge is trapped in the nitride layer. Leakage and charge-trapping efficiency are two major parameters considered in device performance evaluation. Charge-trapping efficiency determines if the memory devices can keep enough charges in the storage nodes after program/erase operation and is reflected in retention characteristics. It is especially critical when the leakage behavior of storage devices is inevitable.
Silicon content in the nitride layer improves the programming and erasing performances but offers poor data retention. Although silicon content plays an important role in charge-trapping efficiency, it does not have same constructive effect on leakage characteristics. The interface between the charge trapping layer with both the top blocking oxide layer and the bottom tunneling oxide layer present both scaling and functional problems despite the silicon content as well as add cost to the manufacturing process.
Semiconductor fabrication processes have made possible the fabrication of advanced integrated circuits on a semiconductor wafer. These semiconductor fabrication processes are complex, requiring extensive control and care to avoid fabricating defective integrated circuits. Moreover, within the advanced integrated circuits, specialized components are utilized to implement particular functionality. As a result, the advanced integrated circuits undergo a first group of semiconductor fabrication processes to fabricate standard components and undergo a second group of semiconductor fabrication processes to fabricate the specialized components.
In particular, a flash memory chip has a memory array and a plurality of support and control circuits. Generally, the memory array is comprised of a plurality of flash memory devices or cells. Each flash memory device includes a stacked gate structure. The support and control circuits are typically comprised of standard components such as MOS (Metal Oxide Semiconductor) transistors having gate structures, whereas the support and control circuits are typically formed in the peripheral area of the flash memory chip.
In the fabrication of the flash memory chip, a first lithographic process, a first etching process, and a resist removal process are performed to form the stacked gate structure of the flash memory device. Separately, a second lithographic process, a second etching process, and the resist removal process are performed to form the gate structure of the MOS transistor. Typically, the stacked gate structure is formed in the core area and then the gate structure is formed in the peripheral area.
The fabrication process damages the stacked gate structure of the flash memory. Methods to repair the damage to some portion of the stacked gate structure further damages other portion of the stacked gate structure, such as the charge trapping layer.
Thus, a need still remains for a memory cell system providing low cost manufacturing, improved yields, improved programming performance, improved erasing performance, and improved data retention of memory in a system. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.